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general description the DS1864 is an sff-8472 multisource agreement (msa)-compliant laser controller/monitor that is ideal for sfp optical-transceiver module designs. it controls laser driver bias and modulation currents through a pair of tem- perature-controlled current-sink dacs. system diagnos- tics are provided by monitoring three analog inputs, v cc , and temperature through the internal temperature sensor. the device also contains all eeprom required by the sff-8472 msa, including all a0h and a2h eeprom. the DS1864? memory map can be configured to be compati- ble with both the ds1852/ds1856 and the ds1859 mem- ory maps. additionally, memory is secured with customer- configurable two-level password protection. eye-safety features are integrated by three fast-trip comparators that monitor transmit-power high, transmit- power low, and bias current. the fast-trip comparators drive a fet driver output to disable the laser in the case of eye safety violation. with its integrated laser driver control, system diagnos- tics, eye-safety features, and internal temperature sen- sor, the DS1864 provides an ideal solution for sfp optical transceiver modules by improving system perfor- mance, reducing board space, and simplifying design. applications sfp optical transceiver modules laser control and monitoring features ? sff-8472 msa compatible ? five monitored channels (temperature, v cc , mon1, mon2, mon3) three external analog inputs (mon1, mon2, mon3) support internal and external calibration enhanced rssi monitoring (26db range, 0.5db accuracy) scalable dynamic range for external analog inputs internal direct-to-digital temperature sensor alarm and warning flags for all monitored channels ? two linear 8-bit current-sink dacs two user-selectable full-scale ranges (0.5ma or 1.5ma) values changeable every 2? ? three fast-trip comparators (tx power high, tx power low, and bias current) for eye safety ? flexible, two level password scheme provides three levels of security ? provides all optional and required sff-8472 msa eeprom (both a0h and a2h memory) ? i 2 c-compatible serial interface ? operates from a 3.3v or 5v supply ? -40? to +95? operating temperature range ? 28-pin tqfn package (5mm x 5mm) DS1864 sfp laser controller and diagnostic ic ______________________________________________ maxim integrated products 1 rev 0; 4/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes lead-free only package. ordering information part temp range pin-package DS1864t -40? to +95? 28 tqfn (5mm x 5mm) DS1864t+ -40? to +95? 28 tqfn (5mm x 5mm) tqfn 5mm x 5mm top view 26 27 25 24 10 9 11 sda intx-f inlos in1 n.c. 12 rselout dac0 dac1 mon1p v cc mon1n n.c. 1 2 tx-f 4 5 6 7 20 21 19 17 16 15 rx-los out1 mon3n rsel tx-d gnd scl gnd 3 18 28 8 v cc n.c. fetg 23 13 mon3p gnd 22 14 mon2 n.c. DS1864 pin configuration typical operating circuit appears at end of data sheet. * purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
DS1864 sfp laser controller and diagnostic ic 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +95?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc relative to ground ...........-0.5v to +6.0v voltage range on inputs relative to ground* .................-0.5v to (v cc + 0.5v) voltage range on dac pins relative to ground*............-0.5v to (v cc + 0.5v) current into dac pins ...........................................................5ma operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature............see ipc/j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.97 5.50 v input logic 0 (sda, scl) v il i il (max) = -10? -0.3 +0.3 x v cc v input logic 1 (sda, scl) v ih i ih (max) = 10? 0.7 x v cc v cc + 0.3 v v il input logic 0 -0.3 0.9 input logic levels (tx-d, inlos, rsel, in1) v ih input logic 1 1.5 v cc + 0.3 v dc electrical characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units supply current i cc (notes 2 and 3) 3 5 ma input leakage (sda, scl) i il -1 +1 ? v ol1 3ma sink current 0.4 low-level output voltage (sda) v ol2 6ma sink current 0.6 v i/o capacitance c i/o for sda/scl 10 pf tx-d pullup resistor r pu t a = +25? 14 20 24 k ? digital power-on reset v pod 1.0 2.2 v analog power-on reset v poa 2.00 2.97 v high-level output voltage (fetg) v oh 4ma source current v cc - 0.4 v cc + 0.3 v low-level output voltage (tx-f, los voltage, fetg) v ol 4ma sink current 0.0 0.4 v input current each i/o pin 0.4 < v i/o < 0.9v cc -10 +10 ? * not to exceed 6.0v.
DS1864 sfp laser controller and diagnostic ic _____________________________________________________________________ 3 analog output characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter description conditions min typ max units range 1 0.5 ma i dac0 and i dac1 range 2 position ffh (note 6) 1.5 ma i d ac 0 and i d ac 1 ( o ff s tate c ur r ent) shutdown or position 00h 10 100 na voltage at i dac0 and i dac1 0.7 v cc v i dac < 50? ?0 ? range 1 i dac > 50? ? % i dac < 50? 10 ? i dac0 and i dac1 accuracy (note 6) range 2 i dac > 50? ? % resolution 0.4 %fs analog voltage monitoring characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units full-scale monitor input at factory setting (note 4) 2.4875 2.5000 2.5125 v full-scale v cc monitor at factory setting (note 5) 6.5208 6.5536 6.5864 v monitor resolution (v cc , ibi, txp, rin) 0.024 %fs mon1p to mon1n fs mon1 (note 7) 0 2.5 v mon1p, mon1n common-mode voltage 0 v cc v mon1p (single-ended) (notes 7 and 8) 2.5 v mon1 fs (factory) (note 7) 2.5 v mon2 fs (factory) (note 7) 2.5 v mon3 fs (factory) v mon3 = 2.5v (note 7) 2.5 v supply accuracy v ccacc (note 7) 0.5 %fs mon1 accuracy mon1 acc (note 7) 0.5 %fs mon2 accuracy mon2 acc (note 7) 0.5 %fs mon3 accuracy mon3 acc (notes 7 and 9) 0.5 %fs dual range disabled 21.5 26.0 monitoring update rate t frame dual range enabled 57 70 ms fast-trip comparator accuracy fc acc ? %fs
DS1864 sfp laser controller and diagnostic ic 4 _____________________________________________________________________ digital thermometer characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units thermometer error t err -40? to +95? (notes 10, 17) -3 +3 ? dual range disabled 57 70 update rate t frame dual range enabled 67 80 ms ac electrical characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units shutdown and faults (see fault and shutdown timing diagrams figures 1 to 10), for fast alarms and sfp management tx-d (to dacs off-state currents) t off figure 4 from tx-d (notes 11, 17) 5s recovery from normal disable (to dacs set values) t on figure 4 from tx-d (notes 12, 17) 0.8 ms recovery after power-up (to dacs set values) t init_dacs figure 9 from v cc = 2.97v (notes 11, 17) 100 ms shutdown response time (to dacs off-state current) t fault figure 5 i bmd > triphi or i bias > trip i bmd < triplo (notes 11, 17) 50 ? recovery from safety fault shutdown (to dacs set values) t initsf figures 6 and 10 from tx-d (notes 11, 17) 50 ms fault reset time (to tx-f = 0) t initr1 figure 2 from tx-d 100 200 ms fault reset time (to tx-f = 0) t initr2 figures 1, 2, 3, and 6 from v cc = 2.97v 100 200 ms fault assert time (to tx-f = 1) t fault figure 5 i bmd > triphi or i bias > trip i bmd < triplo (note 11) 50 ? los assert time t loss_on figure 8 rssi < trip (note 12) 50 ? los deassert time t loss_off figure 8 rssi > trip (note 12) 50 ? ? ? ? ?? ?
DS1864 sfp laser controller and diagnostic ic _____________________________________________________________________ 5 ac electrical characteristics (continued) (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units timing for soft control and status functions tx-d assert time t off time from tx-d set until dacs fall below 10% of nominal (notes 13, 17) 10 ms tx-d deassert time t on time from tx-d cleared until dacs rise above 90% of nominal (notes 13, 17) 50 ms time to initialize, including reset of tx-f t init time from power-on or negation of tx-f using tx-d; serial communication possible 200 ms tx-f assert time t fault time from fault to tx-f set (note 17) 50 ms rx-los assert time t los_on time from occurrence of loss of signal to rx-los set 50 ms rx-los deassert time t los_off time from occurrence of presence of signal to rx-los cleared 50 ms rate-select change time t rate_sel time from change of state of rate-select bit to rate-select output (rselout) pin change 50 ms i 2 c ac electrical characteristics (v cc = 2.97v to 5.5v; t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (see figure 19) parameter symbol conditions min typ max units scl clock frequency f scl (note 14) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 15) 20 + 0.1c b 300 ns sda and scl fall time t f (note 15) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 15) 400 pf eeprom write time t w (note 16) 10 20 ms
DS1864 sfp laser controller and diagnostic ic 6 _____________________________________________________________________ nonvolatile memory characteristics (v cc = 2.97v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units eeprom writes +70? (note 17) 50,000 writes note 1: all voltages are referenced to ground. currents into the ic are positive, and currents out of the ic are negative. note 2: supply current is measured with all logic inputs at their inactive state (sda = scl = v cc ) and driven to well-defined logic levels. all outputs are disconnected. note 3: dac0/dac1 positions programmed to ffh and with outputs floating. note 4: full-scale is user programmable. the maximum voltage that the mon inputs read is approximately full-scale, even if the voltage on the inputs is greater than full-scale. note 5: this voltage defines the maximum range of the analog-to-digital (adc) converter voltage, not the maximum v cc voltage. note 6: accuracy specification includes supply and temperature variations. measured at 1.2v. note 7: %fs refers to calibrated full scale in the case of internal calibration, and uncalibrated full scale in the case of external ca li- bration. uncalibrated full scale is set at the factory and is specified in this data sheet as v cc fs (factory), mon1 fs (factory), mon2 fs (factory), and mon3 fs (factory). calibrated full scale is set by the user, allowing him to change any of these scales for his instrumentation. note 8: when used single-ended, mon1n must be connected to gnd. note 9: 0.5%fs with 0.5db (~11%) accuracy results in 16.4db range. assuming some overlap of the ranges, this scheme should cover the required 26db range. note 10: see figure 14 for thermometer error. note 11: when the dacs are re-enabled, they ramp up to their final values. the ramp up starts from 0 and should not exceed its final value at any point during its initial transient. note 12: this spec is the time it takes, from rssi voltage below the rssi voltage trip threshold, to los asserted high. note 13: measured from the falling clock edge after the stop bit of the write transaction. note 14: i 2 c interface timing shown for is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c stan- dard-mode timing. note 15: c b ? total capacitance of one bus line in picofarads. note 16: eeprom write begins after a stop condition occurs. note 17: this parameter is guaranteed by design.
DS1864 sfp laser controller and diagnostic ic _____________________________________________________________________ 7 timing diagrams t init v cc > 2.97v tx-f tx-d dac0, dac1 figure 1. power-on initialization with tx-d low t init dac0, dac1 v cc > 2.97v tx-f tx-d figure 2. power-on initialization with tx-d asserted t init v cc > 2.97v tx-f tx-d dac0, dac1 insertion figure 3. example of initialization with tx-d low (hot-plug)
DS1864 sfp laser controller and diagnostic ic 8 _____________________________________________________________________ timing diagrams (continued) tx-f tx-d dac0, dac1 t off t on figure 4. tx-d timing during normal operation t fault dac0, dac1 tx-f occurrence of fault tx-d figure 5. detection of transmitter safety fault operation t reset t init dac0, dac1 tx-f occurrence of fault tx-d note: tx-f is also dependent on intx-f. figure 6. successful recovery from transient safety fault condition
DS1864 sfp laser controller and diagnostic ic _____________________________________________________________________ 9 timing diagrams (continued) dac0, dac1 tx-f occurrence of fault tx-d note: tx-f is also dependent on intx-f. t reset t fault t init figure 7. unsuccessful recovery from a transient safety fault condition los occurrence of los t loss_off t loss_on figure 8. timing of los detection dac0, dac1 tx-d t init_dacs figure 9. output enable/power-up dac0, dac1 tx-d t initsf figure 10. output enable/recovery from safety fault shutdown
dac 0 inl (lsb) setting (dec) dac 0 inl (lsb) DS1864a toc07 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0.5ma mode DS1864 sfp laser controller and diagnostic ic 10 ____________________________________________________________________ dac 0 dnl (lsb) setting (dec) dac 0 dnl (lsb) DS1864a toc08 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0.5ma mode dac 0 inl (lsb) setting (dec) dac 0 inl (lsb) DS1864a toc09 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.5ma mode supply current vs. voltage voltage (v) supply current (ma) DS1864a toc01 3.0 3.5 4.0 4.5 5.0 5.5 2.0 2.1 2.2 2.3 2.4 2.5 sda = scl = v cc supply current vs. temperature temperature ( c) supply current ( a) DS1864a toc02 -40-200 20406080100 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 sda = scl = v cc dac voltages = 0.7v dac settings at ffh dacs in 1.5ma mode dacs in 0.5ma mode output current vs. dac 0 setting dac 0 setting (dec) output current (ma) DS1864a toc03 0 50 100 150 200 250 0 0.1 0.2 0.3 0.4 0.5 0.6 0.5ma mode output current vs. dac 0 setting dac 0 setting (dec) output current (ma) DS1864a toc04 0 50 100 150 200 250 0 0.4 0.8 1.2 1.6 2.0 1.5ma mode output current vs. dac 1 setting dac 1 setting (dec) output current (ma) DS1864a toc05 0 50 100 150 200 250 0 0.1 0.2 0.3 0.4 0.5 0.6 0.5ma mode output current vs. dac 1 setting dac 1 setting (dec) output current (ma) DS1864a toc06 0 50 100 150 200 250 0 0.4 0.8 1.2 1.6 2.0 1.5ma mode typical operating characteristics (v cc = +3.3v, t a = 25?, unless otherwise noted.)
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 11 dac 1 inl (lsb) setting (dec) dac 1 inl (lsb) DS1864a toc13 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.5ma mode dac 1 dnl (lsb) setting (dec) dac 1 dnl (lsb) DS1864a toc14 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.5ma mode typical operating characteristics (continued) (v cc = +3.3v, t a = 25?, unless otherwise noted.) dac 0 dnl (lsb) setting (dec) dac 0 dnl (lsb) DS1864a toc10 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 1.5ma mode dac 1 inl (lsb) setting (dec) dac 1 inl (lsb) DS1864a toc11 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0.5ma mode dac 1 dnl (lsb) setting (dec) dac 1 dnl (lsb) DS1864a toc12 0 25 50 75 100 125 150 175 200 225 250 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0.5ma mode dac setting vs. power-up voltage power-up voltage (v) dac current (ma) DS1864a toc15 012345 0 0.10 0.20 0.30 0.40 0.50 programmed dac setting (80h) dac 0, 0.5ma dac 0 current vs. supply voltage supply voltage (v) dac current (ma) DS1864a toc16 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.20 0.40 0.60 0.80 1.00 dac 0, 0.5ma programmed dac setting (ffh) dac 0 current vs. supply voltage supply voltage (v) dac current (ma) DS1864a toc17 3.0 3.5 4.0 4.5 5.0 5.5 0 0.4 0.8 1.2 1.6 2.0 dac 0, 1.5ma programmed dac setting (ffh) dac 1 current vs. supply voltage supply voltage (v) dac current (ma) DS1864a toc18 3.0 3.5 4.0 4.5 5.0 5.5 0.00 0.20 0.40 0.60 0.80 1.00 dac 1, 0.5ma programmed dac setting (ffh)
DS1864 sfp laser controller and diagnostic ic 12 ____________________________________________________________________ dac 1 current vs. function of the voltage on the dac dac 1 voltage (v) dac 1 current (ma) DS1864a toc23 0.7 1.2 1.7 2.2 2.7 3.2 0 0.50 1.00 1.50 2.00 programmed dac setting (ffh) dac 1, 1.5ma dac current at setting 7fh vs. temperature temperature ( c) dac current (ma) DS1864a toc24 -40-200 20406080100 0.00 0.20 0.40 0.60 0.80 1.00 dacs 0 and 1 in 1.5ma mode dacs 0 and 1 in 0.5ma mode monitor fast-trip inl (lsb) setting (dec) monitor quick trip inl (lsb) DS1864a toc25 0 25 50 75 100 125 150 175 200 225 250 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 monitor fast-trip dnl (lsb) setting (dec) monitor quick trip dnl (lsb) DS1864a toc26 0 25 50 75 100 125 150 175 200 225 250 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 lsb error vs. full-scale input normalized full-scale (%) lsb error DS1864a toc27 0 102030405060708090100 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 dac 1 current vs. supply voltage supply voltage (v) dac current (ma) DS1864a toc19 3.0 3.5 4.0 4.5 5.0 5.5 0 0.4 0.8 1.2 1.6 2.0 dac 1, 1.5ma programmed dac setting (ffh) dac 0 current vs. function of the voltage on the dac dac 0 voltage (v) dac 0 current (ma) DS1864a toc20 0.7 1.2 1.7 2.2 2.7 3.2 0 0.20 0.40 0.60 0.80 1.00 dac 0, 0.5ma programmed dac setting (ffh) dac 0 current vs. function of the voltage on the dac dac 0 voltage (v) dac 0 current (ma) DS1864a toc21 0.7 1.2 1.7 2.2 2.7 3.2 0 0.5 1.0 1.5 2.0 programmed dac setting (ffh) dac 0, 1.5ma dac 1 current vs. function of the voltage on the dac dac 1 voltage (v) dac 1 current (ma) DS1864a toc22 0.7 1.2 1.7 2.2 2.7 3.2 0 0.20 0.40 0.60 0.80 1.00 programmed dac setting (ffh) dac 1, 0.5ma typical operating characteristics (continued) (v cc = +3.3v, t a = 25?, unless otherwise noted.)
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 13 pin description pin pin name description 1 rselout open-drain rate-select output 2 sda i 2 c serial data input/output 3 scl i 2 c serial clock input 4 intx-f tx-f input from external device 5 inlos loss of signal input from external device 6 in1 digital input 7 n.c. no connection 8 n.c. no connection 9 gnd ground. all gnd pins must be connected. 10 tx-d transmit disable input. places dac0 and dac1 in high-impedance state. 11 rsel rate select logic input 12 mon3n voltage monitor input, low side. used typically for rssi. 13 mon3p voltage monitor input, high side. used typically for rssi. 14 mon2 voltage monitor input. used typically for transmit power (txp). 15 n.c. no connection 16 mon1n voltage monitor input, low side. used typically for bias sense current (ibias). 17 mon1p voltage monitor input, high side. used typically for bias sense current (ibias). 18 dac1 lookup table-controlled current sink 19 gnd ground. all gnd pins must be connected. 20 dac0 lookup table-controlled current sink 21 v cc power supply. all v cc pins must be connected. 22 n.c. no connection 23 gnd ground. all gnd pins must be connected. 24 fetg logic output driving external fet 25 tx-f open-drain fault output 26 rx-los open-drain loss of signal output 27 out1 open-drain digital output 28 v cc power supply. all v cc pins must be connected.
DS1864 sfp laser controller and diagnostic ic 14 ____________________________________________________________________ functional diagrams sda ad (auxiliary device enable a0h) md (main device enable) r/w data bus address mode select r/w address table select adfix i 2 c interface device address table 01h (ds1852) table 00h (ds1859) eeprom 120 bytes eeprom 8 bytes password protection md mode select r/w address fast alarms and warning limits table select r/w address table select table 04h (ds1852) table 01h (ds1859) sram 8 bytes 80h?7h eeprom 8 bytes 88h?fh non lut control and configuration registgers password protection md password protection logic control signals table select md mask mask temp index dac range select dac disable dac0 temp index dac range select logic control signals alarm and warning flags mint eeprom 59 bytes c0h?bh table 05h configuration and control r/w address table select password protection md eeprom 72 bytes 80h?7h table 03h dac1 lookup table r/w address table select password protection md eeprom 72 bytes 80h?7h table 02h dac0 lookup table auxiliary device gbic memory eeprom 256 bytes data bus ad r/w address md r/w address password protection password protection lower memory eeprom 96 bytes 00h?fh alarm and warning limits sram 32 bytes 60h?fh dac0 lookup table register dac1 lookup table register dac range select dac disable dac1 monitor limits comparator measurement conversion values 13-bit dac mux internal calibration internal temp interrupt fast alarms and warning flags power- on reset dac disable logic control signals startup/shutdown logic* mask *see figures 12 and 13. fast alarms and warning flags fast alarms and warning limits fast-trip comparators adc control v cc gnd los logic* in1 logic* losc invl in1c inv1 los flag v cc rsel logic* selc DS1864 data bus data bus data bus data bus data bus data bus data bus scl rx-los inlos out1 in1 mon3p mon3n mon2 mon1p mon1n v cc rselout rsel tx-f tx-d fetg intx-f figure 11. block diagram, main
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 15 functional diagrams (continued) power-on reset disable dacs inv tx-f intx-f mint hbal flag ltxp flag htxp flag hbwa flag htxp flag htxp enable tx-d txdc hbal flag hbal enable ltxp flag ltxp enable txds v cc r pu fpol v cc fetg r c dq s q c out fault reset timer (130ms) in in out figure 12. block diagram, shutdown in1s in1c inv1 out1 in1 mux invl losc los flag inlos sels selc rselout rsel rx-los 1 0 figure 13. block diagram, outputs
DS1864 sfp laser controller and diagnostic ic 16 ____________________________________________________________________ detailed description the DS1864 manages all system monitoring functions in a fiber-optic data transceiver module in accordance with sff-8472 msa. the ic communicates with a host system through a i 2 c bus, and can be programmed with a unique i 2 c address. the ic offers temperature-controlled lookup tables for its two current-sink dacs. monitoring and calibration functions for supply voltage, temperature and three analog signals are available, as well as programmable alarm and warning flags for these signals which can be used to trigger interrupts based on user-specified limits. the ic also possesses laser shutdown (eye safety) fea- tures such as programmable fast-trip alarms and inter- rupts, in addition to signals such as fetg for laser safety disconnect. the memory is protected by a customizable two-layer password scheme. furthermore, the memory layout can be configured to be compatible with the ds1852/ds1856 or the ds1859. an overview of the DS1864? functions is shown in the block diagram in figure 11. additional DS1864 func- tions are shown in figures 12 and 13. control features the DS1864 contains two current-sink dacs, dac0 and dac1. normally, each dac is controlled by a tempera- ture-indexed lookup table (lut), which can change the dac settings based on the temperature measured by the internal temperature sensor. however, each dac can also be manually programmed by the user. dac0 and dac1 the current-sink dacs are linear and have two user- selectable ranges, 1.5ma and 0.5ma. the range is selected by the dac0r and dac1r bits located in address 88h in table 04h (table 01h in ds1859 config- uration). the 1.5ma range is selected when the corre- sponding bit is set to a 1, and the 0.5ma range is selected when the corresponding bit is set to a 0. the temperature-indexed lut for each dac determines the value to be loaded in to the dac0 and dac1 registers (bytes 82h and 83h respectively in table 04h (table 01h in ds1859 configuration)). the dacs can be disabled (placed in a high-impedance mode) by pulling the tx-d pin high. the txdc control bit (lower memory register, byte 6eh, bit 6) can also be used to disable the dac outputs by placing them in a high-impedance state. to determine the dac position to produce a desired current, the following equation can be used: update bits are provided to indicate when an a/d con- version has completed for each monitored value. these bits are located in lower memory, byte 77h. dac lookup table (lut) operation the current-sink dac settings are determined by tem- perature-controlled lookup tables (luts). the luts are located in table 02h for dac0 and table 03h for dac1. the lookup tables are 72 bytes each and allow the biasing to be adjusted every 2c between -40? and +102?. temperatures less than -40? or greater than +102? use the -40? or +102? values, respec- tively. the values programmed into the luts are 8-bit unsigned values that represent the desired dac setting for each 2? temperature window. the luts have 1? hysteresis (see figure 14) to prevent the dac? setting from chattering in the event the temperature remains near a lut switching point. table 1 shows which regis- ter corresponds to which temperature in the luts. figure 14 shows how the lut chooses which memory location to use for the dacs depending on the temper- ature read from the internal temperature sensor. the temperature index byte (address 81h, table 04h (table 01h in ds1859 configuration)) is automatically calculated following each temperature conversion and points to the corresponding location in the luts for the desired position desired current full scale current = ? ? ? ? ? ? 255 9ah 99h 98h 97h 96h 95h 2 4 6 8 10 12 temperature ( c) memory location increasing temperature decreasing temperature figure 14. lut hysteresis
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 17 current temperature. the dac value referenced in the lut is then loaded into address 82h of table 04h (table 01h in ds1859 configuration) for dac0 and into address 83h of table 04h (table 01h in ds1859 config- uration) for dac1. dac manual mode during normal operation, the dac setting is automati- cally modified once per conversion cycle based on the adc results. however, if the ten bit (bit 1, address 80h, table 04h (table 01h in ds1859 configuration)) is set to 0, the dacs are placed in a manual mode and temperature indexing is disabled. once in manual mode, the user programs the current-sink dacs by writing the desired positions to addresses 82h and 83h in table 04h (table 01h in ds1859 configuration) to control dac0 and dac1, respectively. rsel operation the rate select pin (rsel) along with the selc rate select bit (lower memory register, byte 6eh, bit 3) determine the state of the rselout pin, which is intended to be used to control receiver multirate perfor- mance. the rsel pin state is or?d with the state of the selc bit to determine the rselout pin state. bit sels (lower memory register, byte 6eh, bit 4) indicates the state of the rsel pin. see figure 13 for more details. monitoring features the DS1864 incorporates five basic monitor channels, which include temperature, supply voltage (v cc ), and three external channels (mon1, mon2, and mon3). these analog signals are sampled and converted into digital measurements and compared to threshold limits to determine alarm and warning signals and fault states. these five signals can be calibrated externally, using reserved registers for calibration values, or internally, using built-in gain, offset, and right-shifting functions. digital diagnostics in optical transceiver applications, the external monitor channels are typically used for bias current (ibi) through pins mon1p and mon1n, transmitted power (txp) through a mon2 pin, and received power (rin) through pins mon3p and mon3n. while mon2 is a single-ended monitor, mon1 and 3 have the option of being used as differential or single-ended monitors. to use these channels single-ended, connect the ??side to ground. a 13-bit adc samples and digitizes the five analog signals and the results are stored in registers 60h through 69h in the lower memory. the representa- tive digital values are 13-bits wide (left justified), and are stored in successive register pairs. the tempera- ture value is stored in a 2? complement format, while v cc and the three analog inputs are stored in an un- signed format. the digital values are updated every t frame . from these measurements, alarms and warn- ings are generated after a digital comparison with high and low set limits. a maskable interrupt, mint, asserted through tx-fault, can be enabled based on any combi- nation of alarms and warnings. alarm and warning flags alarm and warning flags are generated by comparing the digitally converted values of the measured tempera- ture, supply voltage, and three mon inputs with user- programmed upper and lower limits. these limits are stored in eeprom locations 00h through 27h in the lower memory. the two types of flags, alarm and warn- ing, are also stored in the lower memory. addresses 70h and 71h contain the alarm flags, while addresses 74h and 75h contain the warning flags. the alarms and warnings section under fault management describe how to program the alarm and warning thresholds, and how to use them to generate interrupts. calibration overview calibration is provided internally or externally. external calibration makes use of a range of registers, reserved for this purpose according to sff-8472 standard. this range is 38h to 5f in the lower memory registers. the calibration constants are loaded in the registers during system test. in external calibration mode, a host processor retrieves the constants and computes the calibrated data. the DS1864 features internal calibration for the five analog channels. internal calibration makes use of two registers for four of the five monitored analog channels: v cc , mon1 (bias current (ibi)), mon2 (transmitted power (txp)) and mon3 (received power (rin)). one register is for offset calibration, the other for gain cali- bration. both registers are loaded during system test. only the offset scaling register is used for temperature. table 1. lut addresses for corresponding temperature values address (hex) corresponding temperature (?) 80 -40? 81 -38? 82 -36? ?? c6 +100? c7 +102?
DS1864 sfp laser controller and diagnostic ic 18 ____________________________________________________________________ internal calibration applies to measured values acquired by the adc, and does not apply to the fast alarms. if inter- nal calibration is desired, each analog channel requires that registers 8eh through afh in table 04h (table 01h in ds1859 configuration) are loaded with the appropriate val- ues to calibrate for gain and offset. every gain and offset register is 2-bytes wide. both gain and offset calibration are independently capable of converting input variables into a digital output range spanning 0000h to ffffh. the last adjustment is made by using right-shifting. right-shifting registers are located in registers a2h through abh and aeh to afh, and store a 3-bit value used to shift each mon value from 0 to 7 spaces to the right. the effect of this is to make better use of the adc range and increase the accuracy of the readings. right- shifting is the last function performed on the mon sig- nal before the digital value is sent to the mon register. temperature monitor operation the internal temperature monitor values are stored in 16-bit 2? complement format, and located in memory addresses 60h and 61h of the lower memory. the tem- perature conversions are updated every t frame , and do not occur during an active read or write to memory. the factory default calibration values for the tempera- ture monitor are shown in table 2. to convert the 2s complement register value to the tem- perature it represents, first convert the 2-byte hexadeci- mal value to a decimal value as if it is an unsigned value, then divide the result by 256. finally, subtract 256 if the result of the division is greater than or equal to +128. example converted values are shown in table 3 below. the offset of the temperature sensor can be adjusted using the internal calibration registers to account for differences between the ambient temperature at the location of the DS1864 and the temperature of the device it is biasing. when offsets are applied to the temperature measurement, the value converted is off- set by a fixed value from the DS1864? ambient temper- ature. for more information, see the following temperature monitor offset calibration section. temperature monitor offset calibration the DS1864? temperature sensor comes precalibrated and requires no further adjustment by the customer for proper operation. however, it is possible to characterize a system and add a fixed offset to the DS1864? temper- ature reading so it is representative of another location? temperature. this is not required for biasing because the temperature offset can be accounted for by adjust- ing the data? location in the luts, but this feature is available for customers that see application benefits. to change the temperature sensor? offset: write the temperature offset register to 0000h, measure the source reference temperature (t ref , ?), and read the temperature from the DS1864 (t DS1864 , ?). then, the following formula can be used to calculate the value for the temperature offset register. once the value is calculated, write it to the temperature offset register. voltage monitor operation in addition to monitoring temperature, the DS1864 mon- itors v cc and the three mon inputs in a round-robin fashion using its 13-bit a/d converter. the converted values are stored in memory addresses 62h to 69h as 16-bit unsigned numbers with the adc results left justi- fied in the register. the round-robin update time is specified by t frame in the analog voltage monitoring characteristics. the default factory-calibrated values for the voltage monitors are shown in table 4. by using the internal gain and offset calibration regis- ters the +fs and -fs signal values shown in table 4 can be modified to meet customer needs. for more information on calibration, see the following voltage monitor calibration section. note: ?s voltages shown in table 4 were calculated assuming factory-programmed gain and offset values in addition to right shifting set to 0. temp offset t t xor bb h ref ds bitwise =?+ ? () 64 275 40 1864 () signal +fs signal +fs (hex) -fs signal -fs (hex) temperature +127.96875? 7ff8 -128.00? 8000 table 2. internal temperature monitor factory default calibration table 3. temperature conversion values msb (bin) lsb (bin) temperature (?) 01000000 00000000 64 01000000 00001111 64.059 01011111 00000000 95 11110110 00000000 -10 11011000 00000000 -40
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 19 to calculate the voltage measured from the register value, first calculate the lsb weight of the 16-bit register. the lsb weight is equal to the full-scale voltage span divided 65528. next, convert the hexadecimal register value to decimal and multiply it times the lsb weight. example: using the factory default v cc trim, what volt- age is measured if the v cc register value is c340h? the lsb for v cc is equal to (6.5528v - 0v) / 65528 = 100.00?. c340h is equal to 49984 decimal, which yields a supply voltage equal to 49984 x 100.00? = 4.9984v. table 5 shows more conversion examples based on the factory trimmed a/d settings. the factory-programmed lsb for v cc is 100?. the factory-programmed lsb weight for the mon channels is 38.147?. voltage monitor calibration (gain, offset, and right shifting) the DS1864 has the ability to scale each analog volt- age? gain and offset to produce the desired digital result. each of the inputs (v cc , mon1, mon2, mon3) has specific registers for the gain, offset, and right shift- ing (in memory table 04h (table 01h in ds1859 config- uration)) allowing them to be individually calibrated. to scale the gain and offset of the converter for a spe- cific input, one must first know the relationship between the analog input and the expected digital result. the input that would produce a digital result of all zeros is the null value (normally this input is gnd). the input that would produce a digital result of all ones (fff8h) is the full-scale (fs) value. the expected fs value is also found by multiplying fff8h by the lsb weight. the right-shifting operation on the a/d converter output is carried out based on the contents of registers right shift1 and right shift2 in eeprom. each of the three analog channels (mon1 (bias current (ibi)), mon2 (transmitted power (txp)), and mon3 (received power (rin)) is allocated 3 bits to set the number of right shifts. up to 7 right-shift operations are allowed and will be executed as a part of every conversion before the result is loaded in the corresponding measurement registers 62h to 69h. this is true during the setup of internal cali- bration as well as during subsequent data conversions. example: since the fs digital reading is 65528 (fff8h) lsbs, if the lsb? weight is 50?, then the fs value is 65528 x 50? = 3.2764v. a binary search is used to calibrate the gain of the con- verter. this requires forcing two known voltages on the input pin. it is preferred that one of the forced voltages is the null input and the other is 90% of fs. since the lsb of the least significant bit in the digital reading register is known, the expected digital results can be calculated for both the null input and the 90% of full-scale value. an explanation of the binary search used to scale the gain is best served with the following example pseudo-code: /* assume that the null input is 0.5v */ /* assume that the requirement for the lsb is 50 v */ fs = 65528 * 50e-6; /*3.2764v */ cnt1 = 0.5 / 50e-6; /* 1000 */ cnt2 = 0.9 x fs / 50e-6; /* 58968 */ /* so the null input is 0.5v and 90% of fs is 2.94876v */ set the input's offset register to zero gain_result = 0h; /* working register for gain calculation */ clamp = fff0h; /* this is the max a/d value*/ for n = 15 down to 0 begin gain_result = gain_result + 2^n; write gain_result to the input's gain register; force the 90% fs input (2.94876v); meas2 = a/d result from DS1864; if meas2 >= clamp then gain_result = gain_result - 2^n; else force the null input (0.5v) meas1 = a/d result from DS1864 if [(meas2-meas1)>(cnt2-cnt1)] then gain_result = gain_result - 2^n; end; write gain_result to the input's gain register; table 4. voltage monitor factory default calibration signal +fs (v) +fs (hex) -fs (v) -fs (hex) v cc 6.5528v fff8 0v 0000 mon1 2.4997v fff8 0v 0000 mon2 2.4997v fff8 0v 0000 mon3 2.4997v fff8 0v 0000 table 5. voltage monitor conversion examples signal lsb weight ?) register value (hex) input voltage (v) v cc 100.00 8080 3.2896 v cc 100.00 c0f0 4.9392 mon1 38.147 aa00 1.6601 mon2 38.147 1880 0.2392 mon3 38.147 9cf0 1.5326
DS1864 sfp laser controller and diagnostic ic 20 ____________________________________________________________________ the gain register is now set and the resolution of the conversion will match the expected lsb. customers requiring nonzero null values (e.g., 0.5v as the example shows) must next calibrate the input? offset. if the desired null value is 0v, leave the offset register pro- grammed to 0000h and skip this step. to calibrate the offset register, program the gain regis- ter with the gain_result value determined above. next, force the null input voltage (0.5v for the example) and read the digital result from the part (meas1). the offset value can be calculated using the following formula: this value is then programmed into the corresponding offset register. enhanced rssi monitoring (dual-range functionality) the DS1864 offers a brand new feature to improve the accuracy and range of mon3, which is most commonly used for monitoring rssi. predecessors of the DS1864, namely the ds1859 and the ds1856, feature program- mable gain, offset, and right shifting (scalable dynamic ranging) on each of the mon channels. these three elements are extremely beneficial when monitoring low- amplitude signals such as rssi. the accuracy of the rssi measurements is increased at the small cost of reduced range (of input signal swing). the DS1864 eliminates this tradeoff by offering ?ual-range?calibra- tion on the mon3 channel. this feature enables right shifting (along with its gain and offset settings) when the input signal is below a set threshold (within the range that benefits using right shifting) and then auto- matically disables right shifting (recalling different gain and offset settings) when the input signal exceeds the threshold. also, to prevent ?hattering,?hysteresis pre- vents excessive switching between modes in addition to ensuring that continuity is maintained. dual-range operation is enabled by default (factory programmed in eeprom). however, it can easily be disabled by the rssif and rssic bits, which are described later in this section. when dual-range operation is disabled, mon3 operates identically to the other mon channels, although featuring a differential input. dual-range functionality consists of two modes of oper- ation: fine mode and course mode. each mode is cali- brated for a unique transfer function, hence the term ?ual range.?table 7 highlights the registers related to mon3. fine mode is equivalent to the other mon chan- nels and is similar to the ds1859 and ds1856. fine mode is calibrated using the gain, offset, and right shifting registers at locations shown in table 7 and is ideal for relatively small analog input voltages. course mode is automatically switched to when the input exceeds the threshold (to be discussed in a subse- quent paragraph). course mode is calibrated using dif- ferent gain and offset registers, but lacks right shifting (since course mode is only used on large input sig- nals). the gain and offset registers for course mode are also shown in table 7. additional information for each of the registers can be found in the memory map. dual-range operation is transparent to the end user. the results of mon3 analog-to-digital conversions are still stored/reported in the same memory locations (68 to 69h, lower memory) regardless of whether the con- version was performed in fine mode or course mode. the only way to tell which mode generated the digital result is by reading the rssis bit. when the DS1864 is powered up, analog-to-digital con- versions begin in a round-robin fashion. every mon3 timeslice begins with a fine mode analog to digital con- version (using fine mode? gain, offset, and right-shift- ing settings). see the flowchart in figure 15. then, depending on whether the last mon3 timeslice resulted in a course mode conversion and also depending on the value of the current fine conversion, decisions are made whether to use the current fine mode conversion result or to make an additional conversion (within the same mon3 timeslice), using course mode (using course mode? gain and offset settings ? and remem- ber, no right shifting) and reporting the course mode result. the flowchart also illustrates how hysteresis is implemented. the fine mode conversion is compared to one of two thresholds. the actual threshold values are a function of the number of right shifts being used. table 6 shows the threshold values for each possible number of right shifts. the rssif and rssic bits are used to force fine mode or course mode conversions, or to disable the dual- range functionality. dual-range functionality is enabled by default (both rssic and rssif are factory pro- grammed to ??in eeprom). it can be disabled by set- ting rssic to 0 and rssif to 1. these bits are also useful when calibrating mon3. for additional informa- tion, see the memory map . fault management the DS1864 provides a variety of system alerts to help automate laser control. these alerts are in the form of fast-trip comparators, fast-trip alarm and warning thresholds, diagnostic alarm and warning thresholds, and configurable laser eye safety and shutdown logic. fast-trip comparator values are measured against fast- trip thresholds to set alarms and to enable fault and offset meas =? ? ? ? ? ? ? 1 1 4
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 21 shutdown signals. alarm and warning thresholds keep the system functioning within user-programmed para- meters. all alarm and warning flags are active high. fast-trip alarms and warnings can be configured to overwrite the diagnostic flags for the same function. laser safety features are also implemented to accept and send alarm signals to control laser activity. fast-trips the three monitor channels (mon1, mon2, and mon3) have associated fast channels. a sequencer with fast-trip comparators monitors the three voltage channels: mon1 (bias current (ibi)), mon2 (transmitted power (txp)), and mon3 (received power (rin)). these signals are the same raw (uncalibrated) signals used for the diagnostic circuits. five fast-trip flags (alarms and warnings) are generated: high-bias alarm (hbal), high-bias warning (hbwa), high transmitted power (htxp), low transmitted power (ltxp), and loss of received signal (los), see figure 12. these flags are located in lower memory, byte 73h. these flags are latched temporarily by design as required by the sequencer. in order to disable a com- parator, set its threshold to 00h for low flags and ffh for high flags. the ft_enable bit (bit 3, byte 80h, table 04h (table 01h in ds1859 configuration)) determines if fast- trip alarms are enabled or disabled. the thresholds for hbal and hbwa can be pro- grammed to be temperature compensated. registers b0h to b7h for hbal and b8h to bfh for hbwa of table 04h (table 01h in ds1859 configuration) are where the temperature-compensated alarm and warn- ing thresholds are stored. register dbh of table 04h (table 01h in ds1859 configuration) is the location of the htxp programmable threshold. register dch of table 7. mon3 configuration registers fine mode course gain register 98 to 99h, table 04h* 9a to 9bh, table 04h* offset register a8 to a9h, table 04h* aa to abh, table 04h* right shift register 8fh, table 04h* n/a rssic and rssif bits 8ah, table 04h* rssis bit 77h, lower memory mon3 measurement 68 to 69h, lower memory * table 04h in ds1852 configuration or table 01h in ds1859 configuration. table 6. mon3 hysteresis threshold values # of right shifts fine mode max (hex) course mode min* (hex) 0 fff8 f000 1 7ffc 7800 2 3ffe 3c00 3 1fff 1e00 4 0fff 0f00 5 07ff 0780 6 03ff 03c0 7 01ff 01e0 * this is the minimum reported course mode conversion. mon3 timeslice end of mon3 timeslice perform fine mode conversion report fine conversion result report course conversion result did prior mon3 timeslice result in a course conv.? (rssis = 1?) rssis bit = 0 rssis bit = 1 was current fine mode conv. < course min? perform course mode conversion did current fine mode conv. reach max? n y y y n n figure 15. dual-range functionality flowchart
DS1864 sfp laser controller and diagnostic ic 22 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration) is the location of the ltxp programmable threshold. register ddh of table 04h (table 01h in ds1859 configuration) is the location of the los programmable threshold. alarms and warnings there are ten comparators for alarms and ten compara- tors for warnings for the five analog channels: v cc , temperature, mon1, mon2, and mon3. these com- parators have high and low threshold limits, which are used to determine when alarm and warning flags are triggered. a high alarm flag occurs when a comparator determines if the monitored analog value is above a programmable threshold. a low alarm flag occurs when a comparator determines if the monitored analog value is below a programmable threshold. the same applies for high and low warning flags, though warning flags are typically set to trip prior to the alarm flags. the pro- grammable thresholds have a 2-byte set point in the same format as the adc values stored in lower memory bytes 60h through 69h. the programmable high and low thresholds for both alarms and warnings are located in lower memory bytes 00h through 27h. the status bits for the alarm flags are located in lower memory bytes 70h and 71h. the status bits for the warning flags are located in lower memory bytes 74h and 75h. a high alarm or warning flag is set to a 1 when the corresponding digital value exceeds the user pro- grammed high threshold. a low alarm or warning flag is set to a 1 when the corresponding digital value goes below the user-programmed low threshold. comparisons of all measured values with high and low alarm and warning limits are done automatically. the mask bits control which flags can assert the mask- able interrupt bit, mint (bit 0, address 71h of the lower memory). the mask bits are located in table 01h, bytes f8h through fbh, or table 05h, bytes f8h through fbh, depending on the state of the mask bit (table 04h (table 01h in ds1859 configuration), byte dah, bit 0). if the mask bit is 0, then the values in addresses f8h through fbh in table 05h will determine which flags will assert mint. if the mask bit is 1, then the values in addresses f8h through fbh in table 01h (table 00h in ds1859 configuration) will determine which flags will assert mint. tx-f, intx-f, and tx-d the tx-f pin is used to indicate a dac shutdown and/or laser fault. see the logic diagram in figure 12. the txdc control bit (bit 6, byte 6eh of the lower memory) is a software-controllable shutdown feature. it not only triggers tx-f to go active when set to a 1, but will also disable the dacs, shutting down the laser. the tx-d pin acts like a hardware version of the txdc bit, triggering the tx-f pin and disabling the dacs when set high. the mint interrupt bit discussed earlier also can trigger the tx-f pin if configured to enable when one of its alarm or warning flags goes high. four fast-trip flags also can trigger tx-f to go active. the intx-f pin, used for trig- gering from an externally generated transmit fault sig- nal, can also be used to trigger the tx-f pin. the inv bit (bit 2, byte 89h, table 04h (table 01h in ds1859 config- uration)) is used to invert the polarity of the tx-f pin. txf bit (bit 2, byte 6eh, lower memory) is a status bit that indicates the state of the output pin tx-f. the tx-f pin is not latched, except in the case of a shutdown fault. the status of tx-f will reset to inactive upon removal of the causes of the alarms, or upon resetting of the shutdown fault. the tx-f pin is open drain. rx-los and inlos the rx-los pin is used to indicate a loss of received signal on the mon3 (received power) input. rx-los can be triggered by either the external signal, inlos, or the internal alarm, los flag. inlos is an input pin that can be used to indicate a loss of signal generated from an external source. los flag (bit 2, byte 73h of lower memory) can also be used to indicate a loss of signal. los flag is active high when the value of mon3 goes below its threshold, set by programming byte ddh of table 04h (table 01h in ds1859 configuration) to the desired limit. to configure which signal triggers rx-los, the losc bit (bit 6, byte 89h, table 04h (table 01h in ds1859 configuration)) is used. if losc = 1, inlos is used to trigger the rx-los indicator. if losc = 0, then the losc flag is used. the final control bit for this logic is the invl bit. the invl bit (bit 0, byte 89h, table 04h (table 01h in ds1859 configuration)) is used to invert the polarity of the rx-los pin. the rx- los pin is open drain. see figure 13 for details. fetg laser safety features an auxiliary shutdown signal fetg can be asserted during a safety fault to disconnect the laser from its supply as a laser safety disconnect. the polarity of this signal is determined by the fpol bit (bit 7, byte dah in table 04h (table 01h in ds1859 configuration)). if fpol is 1, then fetg is high in a shutdown condition. if fpol is 0, then fetg is low in a shutdown condition. a safety fault is a latched event that is generated from the fast-trip flags (ltxp, hbal, and htxp). these flags can be independently configured to initiate a safety fault using the enable bits (bits 4, 5, and 6 in byte dah of table 04h (table 01h in ds1859 configuration)). a 1 for these bits enables that specific flag to generate a safety fault, while a 0 masks the flag. when a safety fault is generated, the dacs are disabled (forced to a high-impedance state), fetg is disabled (driven low),
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 23 and tx-f is set active. a falling edge of transmit disable (the logic or of tx-d/txdc) will initiate a safety fault recovery. at this point, the fetg output and the dacs are enabled. the tx-f output will not be disabled until a t initr1 time later. ltxp is masked during this time peri- od to allow for system recovery. hbal and htxp flags are not masked and will generate another safety fault if their appropriate limit is exceeded. a safety fault is not generated on standard shutdowns (the logic or of tx-d/txdc). power-up and low-voltage operation during power-up, the device is inactive until v cc exceeds the analog power-on-reset (v poa ), at which time the device becomes fully functional. once v cc exceeds v poa , the rdyb bit (address byte 6eh, bit 0) is timed to go from a 1 to a 0 and indicates when a/d conversions begin. if v cc ever dips below v poa , the rdyb bit reads as a 1 again. once a device exceeds v poa and the eeprom is recalled, the values remain active (recalled) until v cc falls below v pod . as the device powers up, the v cc low alarm flag defaults to a 1 until the first v cc a/d conversion occurs and sets or clears the flag accordingly. memory organization the DS1864 memory map is divided into seven sec- tions that include auxiliary memory, lower memory, and five upper memory tables. the upper memory tables are addressed by setting the table select byte (7fh in the lower memory) to the desired table number and accessing the upper memory locations (80h to ffh). the lower memory and auxiliary device can be addressed at any time regardless of the state of the table select byte. the lower memory and table 04h (table 01h in ds1859 configuration) are used to config- ure the DS1864 and read the status of the monitors. memory tables 02h and 03h contain the temperature indexed dac lookup tables. memory tables 05h and 01h (table 00h in ds1859 configuration) contain masks for alarm and warning flags. table 01h (table 00h in ds1859 configuration) also contains password settings. the mode bit (bit 3, byte 89h in table 04h (table 01h in ds1859 configuration)) selects between ds1852/ ds1856-compatible memory configuration or the ds1859-compatible memory configuration. see figures 16 and 17 for more information. die identification DS1864 has an id hard coded in its die. three registers (table 05h, bytes c0h to c2h) are assigned for this fea- ture. two registers are for the device id, and a third register is for the version number. id registers are hard- wired at the time of manufacture and are globally read- able through the i 2 c interface. memory map configurations the default DS1864 memory configuration is compati- ble with the ds1852 memory map. the mode bit (bit 3, register 89h of table 04h (table 01h in ds1859 config- uration)) can be selected to make the DS1864 memory map compatible with the ds1859 memory map. figure 16 shows the ds1852/ds1856 compatible configuration (default), and figure 17 shows the ds1859-compatible configuration. when the DS1864 is in the ds1852-compatible configu- ration, user memory is in table 01h. in contrast, when the DS1864 is in the ds1859-compatible configuration (having set mode to 1), user memory is in table 00h. in addition, table 04h in the ds1852 configuration will be reassigned as table 01h in the ds1859 configuration. memory protection and passwords the memory of the DS1864 is protected by two pass- words, pw1 (user password) and a pw2 (vendor pass- word). the password entry location for both passwords is in 7bh-7eh of lower memory and resides in sram. the pw2 password setting locations are in table 04h (table 01h in ds1859 configuration), registers c1h to c6h. the pw1 password settings are in table 05h, reg- isters d1h to d6h. password setting and password entry bytes are write only (read as 0s). furthermore, the auxiliary memory and main device memory are divided into eight blocks; see table 9. the read and write protection for each block is activated by an enable bit. two sets of enable bytes are used for both pw1 and pw2 level access, one byte to allow read access to the memory blocks and one byte for write access to the memory blocks. the two pw2 password enable bytes are located in table 04h (table 01h in ds1859 configuration), registers c1h and c2h. the pw1 password enable bytes are located in table 05h, registers d1h and d2h. table 8 shows how the pass- word enable bytes can be configured to protect the memory blocks. table 9 shows the bit assignments for each of the eight blocks of DS1864 memory. see the registers mentioned above in the memory map section for more details. note that regardless of read/write permissions for a given table, password settings and password entry are unconditionally read protected. they are write protect- ed if the proper write enable bit is set to 1. bytes 78h to 7fh in lower memory are unprotected.
DS1864 sfp laser controller and diagnostic ic 24 ____________________________________________________________________ eeprom write disable the see control bit resides in table 04h (table 01h in ds1859 configuration), register 80h, bit 2. by default ( see bit = 0) these locations act as ordinary eeprom. by setting see = 1, these locations function as sram memory allowing an infinite number of write cycles. this also eliminates the requirement for the eeprom write time. because changes made with see = 1 do not effect the eeprom, these changes will not be retained through power cycles. the power-up value will be the last value written with see = 0. table select byte password entry (pwe) (4 bytes) 7fh i 2 c address a2h (default) i 2 c address a0h 00h ffh f7h ffh 80h f8h 00h lower memory eeprom (120 bytes) c7h 80h dac0 lookup table (72 bytes) dac1 lookup table (72 bytes) c7h 80h fbh c0h control and configuration dfh 80h table 01h table 02h table 03h table 05h table 04h non lookup table control and configuration registers gbic eeprom (256 bytes) eeprom (8 bytes) main device auxiliary device note 1: when mode bit (table 04h byte 89h bit 3) = 0, the DS1864 is in ds1852/ds1856-compatible configuration (default). note 2: if adfix = 0, then the main device i 2 c slave address is a2h. f adfix = 1, then the main device i 2 c slave address is determined by the value in 8ch table 04h (in ds1852 configuration). note 3: table 00h does not exist in ds1852/ds1856 configuration. figure 16. ds1852/ds1856-compatible configuration (mode bit = 0, default)
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 25 table select byte password entry (pwe) (4 bytes) 7fh i 2 c address a2h (default) i 2 c address a0h 00h ffh f7h ffh 80h f8h 00h lower memory eeprom (120 bytes) c7h 80h dac0 lookup table (72 bytes) dac1 lookup table (72 bytes) c7h 80h fbh c0h control and configuration table 00h table 02h table 03h table 05h dfh 80h table 01h non lookup table control and configuration registers gbic eeprom (256 bytes) eeprom (8 bytes) main device auxiliary device note 1: when mode bit (table 04h byte 89h bit 3) = 1, the DS1864 is in ds1859-compatible configuration. note 2: if adfix = 0, then the main device i 2 c slave address is a2h. f adfix = 1, then the main device i 2 c slave address is determined by the value in 8ch table 01h (in ds1859 configuration). note 3: table 04h does not exist in ds1859 configuration. figure 17. ds1859-compatible configuration (mode bit = 1)
DS1864 sfp laser controller and diagnostic ic 26 ____________________________________________________________________ table 8. password-enable chart enable bit enable bit status pw2 (c1h, c2h) table 04h (table 01h in ds1859 configuration) pw1 (d1h, d2h), table 05h ? 00 unprotected 01 pw1 password protected 1x pw2 password protected table 9. memory block assignments memory block (range) a0h (00h to 7fh) auxiliary device lower memory a0h (80h to ffh) auxiliary device upper memory a2h (00h to 7ah) main device lower memory a2h (80h to f7h) table 01h* a2h (f8h to ffh) table 01h* a2h (80h to c7h) table 04h and tables* 02h, 03h a2h (f8h to ffh) table 05h a2h (d0h to d6h) table 05h enable bit locations 01234567 * table 01h becomes table 00h in ds1859 configuration. table 04h becomes table 01h in ds1859 configuration.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 27 auxiliary registers 00h to ffh: gbic memory factory default: 00h memory type: eeprom these registers are used to store gbic data as called out by the sff-8472 specification. this block of eeprom is accessed through i 2 c slave address a0h. lower memory register 00h to 01h: high temperature alarm limit factory default: 0000h memory type: shadowed memory (see) 00h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements above this threshold will set its corresponding alarm bit (lower memory register 70h, bit 7). measurements below this threshold will automatically clear its alarm bit. lower memory register 02h to 03h: low temperature alarm limit factory default: 0000h memory type: shadowed memory (see) 02h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements below this threshold will set its corresponding alarm bit (lower memory register 70h, bit 6). measurements above this threshold will automatically clear its alarm bit. lower memory register 04h to 05h: high temperature warning limit factory default: 0000h memory type: shadowed memory (see) 04h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements above this threshold will set its corresponding warning bit (lower memory register 74h, bit 7). measurements below this threshold will automatically clear its warning bit. a0h auxiliary device memory register descriptions memory map a2h main device, lower memory register descriptions
DS1864 sfp laser controller and diagnostic ic 28 ____________________________________________________________________ lower memory register 06h to 07h: low temperature warning limit factory default: 0000h memory type: shadowed memory (see) 06h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 temperature measurements below this threshold will set its corresponding warning bit (lower memory register 74h, bit 6). measurements above this threshold will automatically clear its warning bit. lower memory register 08h to 09h: high v cc alarm limit factory default: 0000h memory type: shadowed memory (see) 08h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the v c c i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 70h, b i t 5) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 0ah to 0bh: low v cc alarm limit factory default: 0000h memory type: shadowed memory (see) 0ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 voltage measurements of the v cc input below this threshold will set its corresponding alarm bit (lower memory register 70h, bit 4). measurements above this threshold will automatically clear its alarm bit. lower memory register 0ch to 0dh: high v cc warning limit factory default: 0000h memory type: shadowed memory (see) 0ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the v cc i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 5) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 29 lower memory register 0eh to 0fh: low v cc warning limit factory default: 0000h memory type: shadowed memory (see) 0eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the v c c i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 4) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t. lower memory register 10h to 11h: high mon1 alarm limit factory default: 0000h memory type: shadowed memory (see) 10h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 11h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 1 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 70h, b i t 3) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 12h to 13h: low mon1 alarm limit factory default: 0000h memory type: shadowed memory (see) 12h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 13h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 1 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 70h, b i t 2) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 14h to 15h: high mon1 warning limit factory default: 0000h memory type: shadowed memory (see) 14h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 15h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 1 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 3) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t.
DS1864 sfp laser controller and diagnostic ic 30 ____________________________________________________________________ lower memory register 16h to 17h: low mon1 warning limit factory default: 0000h memory type: shadowed memory (see) 16h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 17h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 1 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 2) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t. lower memory register 18h to 19h: high mon2 alarm limit factory default: 0000h memory type: shadowed memory (see) 18h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 19h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 2 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 70h, b i t 1) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 1ah to 1bh: low mon2 alarm limit factory default: 0000h memory type: shadowed memory (see) 1ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 2 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 70h, b i t 0) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 1ch to 1dh: high mon2 warning limit factory default: 0000h memory type: shadowed memory (see) 1ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 2 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 1) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 31 lower memory register 1eh to 1fh: low mon2 warning limit factory default: 0000h memory type: shadowed memory (see) 1eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 2 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 74h, b i t 0) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t. lower memory register 20h to 21h: high mon3 alarm limit factory default: 0000h memory type: shadowed memory (see) 20h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 21h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 3 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 71h, b i t 7) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 22h to 23h: low mon3 alarm limit factory default: 0000h memory type: shadowed memory (see) 22h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 23h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 3 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng al ar m b i t ( low er m em or y reg i ster 71h, b i t 6) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts al ar m b i t. lower memory register 24h to 25h: high mon3 warning limit factory default: 0000h memory type: shadowed memory (see) 24h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 25h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 3 i np ut ab ove thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 75h, b i t 7) . m easur em ents b el ow thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t.
DS1864 sfp laser controller and diagnostic ic 32 ____________________________________________________________________ lower memory register 26h to 27h: low mon3 warning limit factory default: 0000h memory type: shadowed memory (see) 26h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 27h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 v ol tag e m easur em ents of the m on 3 i np ut b el ow thi s thr eshol d w i l l set i ts cor r esp ond i ng w ar ni ng b i t ( low er m em or y reg i ster 75h, b i t 6) . m easur em ents ab ove thi s thr eshol d w i l l automatically cl ear i ts w ar ni ng b i t. lower memory register 28h to 37h: reserved memory 28h to 37h reserved lower memory register 38h to 5fh: external calibration constants factory default: 00h memory type: nonvolatile (eeprom) 38h to 5fh eeprom if external calibration constants are used for calibrating the transceiver module, they can be stored in this section of memory , reserved for such use under sff-8472. lower memory register 60h to 61h: measured temperature factory default: n/a memory type: volatile (sram) 60h s2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit7 bit0 signed 2? complement direct-to-digital temperature measurement. lower memory register 62h to 63h: measured v cc factory default: n/a memory type: volatile (sram) 62h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 unsigned voltage measurement of v cc .
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 33 lower memory register 64h to 65h: measured mon1 factory default: n/a memory type: volatile (sram) 64h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 65h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 unsigned voltage measurement of mon1 signal. lower memory register 66h to 67h: measured mon2 factory default: n/a memory type: volatile (sram) 66h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 67h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 unsigned voltage measurement of mon2 signal. lower memory register 68h to 69h: measured mon3 factory default: n/a memory type: volatile (sram) 68h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 69h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 unsigned voltage measurement of mon3 signal. lower memory register 6ah to 6dh: reserved memory 6ah to 6d h reserved
DS1864 sfp laser controller and diagnostic ic 34 ____________________________________________________________________ lower memory register 6eh: logic states power-on value: x0xx0xxx b memory type: volatile (sram) write access n/a all n/a n/a all n/a n/a n/a 6eh txds txdc in1s sels selc txf rxl rdyb bit7 bit0 bit7 txds: tx-disable status bit. indicates the state of the tx-d pin. 0 = tx-d pin is low. 1 = tx-d pin is high. bit6 txdc: soft tx-disable bit. a control bit set by the user in order to control the on/off state of both dac outputs. 0 = dacs enabled (default). 1 = forces the dac0 and dac1 outputs to a high-impedance (off) mode. bit5 in1s: a status bit reflecting the state of the in1 input pin. bit4 sels: a status bit reflecting the state of the rsel input pin. bit3 selc: soft rate select. a control bit that set by the user and or? with sels to set the state of the reselout pin. used for bandwidth selection. 0 = (default) 1 = this bit allows software control over the state of the reselout pin. bit2 txf: a status bit that indicates the state of tx-f output pin. 0 = tx-f pin is at logic 0 1 = tx-f pin is at logic 1 bit1 rxl: a status bit that indicates the state of rx-los input pin. 0 = rx-los pin is at logic 0 1 = rx-los pin is at logic 1 bit0 rdby: ready bar. 0 = v cc is above poa. 1 = v cc is below poa. lower memory register 6fh: reserved memory 6fh reserved for sff-8079
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 35 lower memory register 70h: alarm flags power-on value: determined after each channel? first analog-to-digital conversion. memory type: volatile (sram) 70h tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 bit7 tmpalmhi: high alarm status for temperature measurement. 0 = temperature measurement is below set limit. 1 = temperature measurement is above set limit. bit6 tmpalmlo: low alarm status for temperature measurement. 0 = temperature measurement is above set limit. 1 = temperature measurement is below set limit. bit5 v cc almhi: high alarm status for v cc measurement. 0 = v cc measurement is below set limit. 1 = v cc measurement is above set limit. bit4 v cc almlo: low alarm status for v cc measurement. 0 = v cc measurement is above set limit. 1 = v cc measurement is below set limit. bit3 mon1almhi: high alarm status for mon1 measurement. 0 = mon1 measurement is below set limit. 1 = mon1 measurement is above set limit. bit2 mon1almlo: low alarm status for mon1 measurement. 0 = mon1 measurement is above set limit. 1 = mon1 measurement is below set limit. bit1 mon2almhi: high alarm status for mon2 measurement. 0 = mon2 measurement is below set limit. 1 = mon2 measurement is above set limit. bit0 mon2almlo: low alarm status for mon2 measurement. 0 = mon2 measurement is above set limit. 1 = mon2 measurement is below set limit.
DS1864 sfp laser controller and diagnostic ic 36 ____________________________________________________________________ lower memory register 71h: alarm flags power-on value: determined after each channel? first analog-to-digital conversion. memory type: volatile (sram) 71h mon3hi mon3lo reserved mint bit7 bit0 bit7 mon3almhi: high alarm status for mon3 measurement. 0 = mon3 measurement is below set limit. 1 = mon3 measurement is above set limit. bit6 mon3almlo: low alarm status for mon3 measurement. 0 = mon3 measurement is above set limit. 1 = mon3 measurement is below set limit. bit5:1 reserved bit0 mint: maskable interrupt. an interrupt output signal that is determined by unmasked alarm and warning flags. masks of alarm and warning flags are located in table 01h (table 00h in ds1859 configuration), bytes f8h through fbh, or table 05h, bytes f8h through fbh, depending on the state of the mask bit (table 04h (table 01h in ds1859 configuration), byte dah, bit 0), and determine the state of mint. mint is maskable to 0 if no interrupt is desired by setting bytes f8h through fbh to a value of 00h. lower memory register 72h: reserved memory 72h reserved
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 37 lower memory register 73h: fast-trip flags power-on value: 00h memory type: volatile (sram) 73h 000 hbwa flag hbal flag los flag ltxp flag htxp flag bit7 bit0 these are the results from the fast-trip comparators. if these flags are latched, they can be cleared by writing the flags to 0 . bit7:5 these bits are set to 0. bit4 hbwa flag: fast-trip flag indicating the high bias warning limit has been exceeded. 0 = bias measurement is below set limit. 1 = bias measurement is above set limit. bit3 hbal flag: fast-trip flag indicating the high bias alarm limit has been exceeded. 0 = bias measurement is below set limit. 1 = bias measurement is above set limit. bit2 los flag: fast-trip flag indicating the loss of signal limit has been exceeded. 0 = los measurement is above set limit. 1 = los measurement is below set limit. bit1 ltxp flag: fast-trip flag indicating the low transmit power limit has been exceeded. 0 = rssi measurement is above set limit. 1 = rssi measurement is below set limit. bit0 htxp flag: fast-trip flag indicating the high transmit power limit has been exceeded. 0 = rssi measurement is below set limit. 1 = rssi measurement is above set limit.
DS1864 sfp laser controller and diagnostic ic 38 ____________________________________________________________________ lower memory register 74h: warning flags power-on value: determined after each channel? first analog-to-digital conversion. memory type: volatile (sram) 74h tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 bit7 tmpwrnhi: high warning status for temperature measurement. 0 = temperature measurement is below set limit. 1 = temperature measurement is above set limit. bit6 tmpwrnlo: low warning status for temperature measurement. 0 = temperature measurement is above set limit. 1 = temperature measurement is below set limit. bit5 v cc wrnhi: high warning status for v cc measurement. 0 = v cc measurement is below set limit. 1 = v cc measurement is above set limit. bit4 v cc wrnlo: low warning status for v cc measurement. 0 = v cc measurement is above set limit. 1 = v cc measurement is below set limit. bit3 mon1wrnhi: high warning status for mon1 measurement. 0 = mon1 measurement is below set limit. 1 = mon1 measurement is above set limit. bit2 mon1wrnlo: low warning status for mon1 measurement. 0 = mon1 measurement is above set limit. 1 = mon1 measurement is below set limit. bit1 mon2wrnhi: high warning status for mon2 measurement. 0 = mon2 measurement is below set limit. 1 = mon2 measurement is above set limit. bit0 mon2wrnlo: low warning status for mon2 measurement. 0 = mon2 measurement is above set limit. 1 = mon2 measurement is below set limit.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 39 lower memory register 75h: warning flags power-on value: determined after each channel? first analog-to-digital conversion. memory type: volatile (sram) 75h mon3hi mon3lo reserved bit7 bit0 bit7 monwrn3hi: high warning status for mon3 measurement. 0 = mon3 measurement is below set limit. 1 = mon3 measurement is above set limit. bit6 mon3wrnlo: low warning status for mon3 measurement. 0 = mon3 measurement is above set limit. 1 = mon3 measurement is below set limit. bit5:0 reserved lower memory register 76h: reserved memory 76h reserved
DS1864 sfp laser controller and diagnostic ic 40 ____________________________________________________________________ lower memory register 77h: conversion updates power-on value: 00h memory type: volatile (sram) 77h tau v cc u mon1u mon2u mon3u 0 0 rssis bit7 bit0 each of the status bits becomes a 1 after an update has occurred for the corresponding measurement. the user can write any of the status bits to a 0 and monitor for a transition to a 1 to verify that a measurement has occurred. bit7 tau: temperature measurement update status bit. 0 = temperature measurement has not yet been updated. 1 = temperature measurement has been updated. bit6 v cc u: v cc measurement update status bit. 0 = v cc measurement has not yet been updated. 1 = v cc measurement has been updated. bit5 mon1u: mon1 measurement update status bit 0 = mon1 measurement has not yet been updated. 1 = mon1 measurement has been updated. bit4 mon2u: mon2 measurement update status bit. 0 = mon2 measurement has not yet been updated. 1 = mon2 measurement has been updated. bit3 mon3u: mon3 measurement update status bit. 0 = mon3 measurement has not yet been updated. 1 = mon3 measurement has been updated. bit2 this status bit is set to 0. bit1 this bit is reserved and reads as 0. bit0 rssis: indicates which range is being reported for mon3 internal calibration. 0 = fine range is being reported. 1 = coarse range is being reported. lower memory register 78h to 7ah: reserved memory 78h to 7ah reserved
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 41 lower memory register 7bh to 7eh: password entry bytes power-on value: 0000 0000h memory type: volatile (sram) 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 the password is entered into the four bytes to gain pw1 or pw2 level access. there are two levels of passwords for the DS1864. the lower level password (pw1) will have access to unprotected areas plus those made available with pw1. the higher level password (pw2) will have all of the access of pw1 plus those made available with pw2. see the memory protection section for details on password access. lower memory register 7fh: table select byte power-on value: see below memory type: volatile (sram) 7fh 000002 2 2 1 2 0 bit7 bit0 the upper memory tables of the DS1864 are selected by writing the desired table value in this register. for example, if table 0 4h is to be selected, the value 04h will be written to register 7fh. the power on value of the table select byte is determined by the value written in table 04h (table 01h in ds1859 configuration), register c7h. table 01h (table 00h in ds1859 configuration), 80h to f7h: user memory factory default: 00h memory type: nonvolatile (eeprom) 80h to f7h eeprom bit7 bit0 this is general use eeprom. table 01h in default ds1852 configuration, (table 00h in ds1859 configuration) register descriptions
DS1864 sfp laser controller and diagnostic ic 42 ____________________________________________________________________ table 01h (table 00h in ds1859 configuration), f8h: alarm masks factory default: 00h memory type: shadowed memory (see) f8h tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 bytes f8h and f9h configure a maskable interrupt, determining which alarm flags assert the mint bit (lower memory, byte 71h, bi t 0). if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be wri tten to a 0. these bit locations do not match the register locations as called out in the sff-8472, therefore another four byte set is also stored in table 05h, registers f8h to fbh. the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0 ) determines which of these mask sets is used to generate the mint interrupt. bit7 tmpalmhimask: determines if an interrupt is generated for a high temperature alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 tmpalmlomask: determines if an interrupt is generated for a low temperature alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5 v cc almhimask: determines if an interrupt is generated for a high v cc alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit4 v cc almlomask: determines if an interrupt is generated for a low v cc alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit3 mon1almhimask: determines if an interrupt is generated for a high mon1 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit2 monalmlomask: determines if an interrupt is generated for a low mon1 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit1 mon2almhimask: determines if an interrupt is generated for a high mon2 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit0 mon2almlomask: determines if an interrupt is generated for a low mon2 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 43 table 01h (table 00h in ds1859 configuration), f9h: alarm masks factory default: 00h memory type: shadowed memory (see) f9h mon3hi mon3lo reserved bit7 bit0 these bytes configure a maskable interrupt, determining which alarm flags assert the mint bit (lower memory, byte 71h, bit 0). if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. these bit locations do not match the register locations as called out in the sff-8472, therefore another four byte set is also stored in another location (table 05h, registers f8h to fbh). the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which mask sets is used to generate the mint interrupt. bit7 monalm3himask: determines if an interrupt is generated for a high mon3 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 mon3almlomask: determines if an interrupt is generated for a low mon3 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5:0 reserved.
DS1864 sfp laser controller and diagnostic ic 44 ____________________________________________________________________ table 01h (table 00h in ds1859 configuration), fah: warning masks factory default: 00h memory type: shadowed memory (see) fah tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 these bytes configure a maskable interrupt, determining which warning flags assert the mint bit (lower memory, byte 71h, bit 0) . if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. these bit locations do not match the register locations as called out in the sff-8472, therefore another four byte set is also stored in another location (table 05h, registers f8h to fbh). the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which of these mask sets is used to generate the mint interrupt. bit7 tmpwrnhimask: determines if an interrupt is generated for a high temperature warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 tmpwrnlomask: determines if an interrupt is generated for a low temperature warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5 v cc wrnhimask: determines if an interrupt is generated for a high v cc warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit4 v cc wrnlomask: determines if an interrupt is generated for a low v cc warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit3 mon1wrnhimask: determines if an interrupt is generated for a high mon1 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit2 monwrnlomask: determines if an interrupt is generated for a low mon1 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit1 mon2wrnhimask: determines if an interrupt is generated for a high mon2 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit0 mon2wrnlomask: determines if an interrupt is generated for a low mon2 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 45 table 01h (table 00h in ds1859 configuration), fbh: warning masks factory default: 00h memory type: shadowed memory (see) fbh mon3hi mon3lo reserved bit7 bit0 these bytes configure a maskable interrupt, determining which warning flags assert the mint bit (lower memory, byte 71h, bit 0) . if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. these bit locations do not match the register locations as called out in the sff-8472, therefore another four byte set is also stored in another location (table 05h, registers f8h to fbh). the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which mask sets is used to generate the mint interrupt. bit7 mon3wrnhimask: determines if an interrupt is generated for a high mon3 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 mon3wrnlomask: determines if an interrupt is generated for a low mon3 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5:0 reserved. table 01h (table 00h in ds1859 configuration), fch to ffh: general memory factory default: 00h memory type: shadowed memory (see) fc h to ffh eeprom bit7 bit0 this is memory reserved for general use. table 02h, 80h to c7h: temperature lookup table for dac0 factory default: 00h memory type: nonvolatile (eeprom) 80h to c7h eeprom bit7 bit0 this is the lookup table (lut) for the dac0 settings. table 02h register descriptions
DS1864 sfp laser controller and diagnostic ic 46 ____________________________________________________________________ table 03h, 80h to c7h: temperature lookup table for dac1 factory default: 00h memory type: nonvolatile (eeprom) 80h to c7h eeprom bit7 bit0 this is the lookup table (lut) for the dac1 settings. table 04h (table 01h in ds1859 configuration), 80h: mode power-on value: 0bh memory type: volatile (sram) 80h 0000 ft_enable see ten aen bit7 bit0 this byte controls the different modes of the DS1864. it controls the analog-to-digital updates, the shadowed eeprom functional ity and the fast-trip comparators. bit7:4 value is 0. bit3 ft_enable: determines if the fast-trip comparators used to set fast-trip alarms are enabled or disabled. 0 = fast-trips are disabled. 1 = fast-trips are enabled. bit2 see : determines if the shadowed eeprom acts like sram or eeprom. 0 = acts like eeprom (nonvolatile). 1 = acts like sram (volatile). bit1 ten: determines if the temperature conversions are enabled or disabled. 0 = temperature conversions disabled. dac0 and dac1 settings can be controlled manually by writing to registers 82h and 83h in table 04h (table 01h in ds1859 configuration). 1 = temperature conversions enabled. lookup tables in automatic control mode. (default) bit0 aen: determines if the address calculations from the lut are enabled or disabled. this bit controls a test mode setting that can allow manual control over the temperature index, table 04h (table 01h in ds1859 configuration), register 81h. 0 = test mode. manual control over temperature index enabled. 1 = normal operation. temperature index calculations automatically carried out. table 04h (table 01h in ds1859 configuration), 81h: temperature index byte factory default: 00h until first temperature conversion. memory type: volatile (sram) 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte is the temperature calculated index used to select the address of dac settings in the lookup tables. table 04h in default ds1852 configuration, (table 01h in ds1859 configuration) register descriptions table 03h register descriptions
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 47 table 04h (table 01h in ds1859 configuration), 82h: dac0 value factory default: dac0 value is high-impedance (hi-z) until programmed value is recalled from memory type: volatile (sram) 82h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 dac values from 00h to ffh for dac0 are stored here. under normal operation, the luts automatically select the dac setting according to the values programmed into the corresponding lut. this byte is updated automatically based on the current temperature and is corresponding setting in the lut. table 04h (table 01h in ds1859 configuration), 83h: dac1 value factory default: dac1 value is high-impedance (hi-z) until programmed value is recalled from memory type: volatile (sram) 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 dac values from 00h to ffh for dac1 are stored here. under normal operation, the luts automatically select the dac setting according to the values programmed into the corresponding lut. this byte is updated automatically based on the current temperature and is corresponding setting in the lut. table 04h (table 01h in ds1859 configuration), 84h to 87h: reserved memory 84h to 87h reserved
DS1864 sfp laser controller and diagnostic ic 48 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), 88h: configuration and status factory default: 00h memory type: shadowed memory (see) 88h in1c x inv1 ft_latch dac1r dac0r alatch wlatch bit7 bit0 bit7 in1c: software control bit for in1 value. 0 = no interrupt is generated on out1. 1 = an interrupt is generated on out1. bit6 no function. bit5 in v1 : al l ow s i nver si on of ou t1 p i n val ue. ou t1= in v 1[ ( in 1c ) or( in 1s ) ] , w her e in 1s i s fr om r eg i ster 6e h. 0 = no interrupt is generated. 1 = an interrupt is generated. bit4 ft_latch: configures fast-trip flags to be latched or unlatched. 0 = fast-trip flags unlatched. 1 = fast-trip flags latched. they will clear when written to 0?. bit3 dac1r: range select for dac1. 0 = the 0.5ma range is selected. 1 = the 1.5ma range is selected. bit2 dac0r: range select for dac0. 0 = the 0.5ma range is selected. 1 = the 1.5ma range is selected. bit1 alatch: alarm latch. configures alarm flags to be latched or unlatched. 0 = alarm flags unlatched. 1 = alarm flags latched. they will clear when written to 0s. bit0 wlatch: warning latch. configures warning flags to be latched or unlatched. 0 = warning flags unlatched. 1 = warning flags latched. they will clear when written to 0s.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 49 table 04h (table 01h in ds1859 configuration), 89h: logic configuration factory default: 00h memory type: shadowed memory (see) 89h x losc x adfix mode inv x invl bit7 bit0 logic control bits for alarm and warning flags, as well as internal and external signals. bit7 this bit is not used. bit6 losc: a los channel configuration bit. 0 = the analog signal mon3, resulting from rssi, is compared to a threshold, asserting los if it is lower than the threshold. 1 = a digital input signal, inlos, is used as the source for the los signal. bit5 this bit is not used. bit4 adfix: determines which i 2 c slave address is used. 0 = a2h i 2 c address selected (default). 1 = i 2 c address determined by value in table 04h (table 01h in ds1859 configuration), register 8ch. bit3 mode: selects between ds1852/ds1856 memory configuration or ds1859 memory configuration. the next i 2 c command will be to the selected configuration if a change is made. does not require a power cycle. 0 = ds1852 configuration selected (default). 1 = ds1859 configuration selected. bit2 inv: used for polarity inversion or non-inversion if an externally generated txf is used. see figure 12. tx-f=[inv[xor]intxf] bit1 this bit is not used. bit0 invl: used for polarity inversion or non-inversion if an externally generated inlos signal is used. rxlos=[invl[xor]inlos] table 04h (table 01h in ds1859 configuration), 8ah: configuration factory default: 00h memory type: shadowed memory (see) 8ah x x x x x x rssic rssif bit7 bit0 for ces coar se or fi ne m easur em ent for m on 3 ( rs s i) i np ut. n ote: d ual - r ang e functi onal i ty can b e d i sab l ed b y w r i ti ng thi s r eg i ster to 01h. bit7:2 no function. bit1 rssic: force the dual range conversion to use coarse measurement only. this is used for calibration of mon3. 0 = coarse measurement not forced. 1 = c oar se m easur em ent for ced . if b oth rs s ic and rs s if ar e 1, then the c oar se m easur em ent i s used . bit0 rssif: force the dual range conversion to use fine measurement only. this is used for calibration of mon3. 0 = fine measurement not forced. 1 = fine measurement forced. if both rssic and rssif are 1, then the coarse measurement is used.
DS1864 sfp laser controller and diagnostic ic 50 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), 8bh: reserved memory 8bh reserved table 04h (table 01h in ds1859 configuration), 8ch: main device address factory default: a2h memory type: shadowed memory (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 contains the main device address. if adfix = 1, then the value in this register determines the i 2 c slave address for the main device memory. if adfix = 0, the slave address is a2h. there are 128 possible addresses that can be programmed. if adfix = 1 and this register was changed to a0h, gbic memory will not be addressed. table 04h (table 01h in ds1859 configuration), 8dh: reserved memory 8d h reserved table 04h (table 01h in ds1859 configuration), 8eh: right-shift control factory default: 00h memory type: shadowed memory (see) 8eh reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 bit7 bit0 control right shifts for the monitor channels. bit7 reserved bit6:4 mon1 2 -mon1 0 : allows for right-shifting the final answer of mon1 voltage measurements. allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the reading is weighted to the correct lsb. bit3 reserved bit2:0 mon2 2 -mon2 0 : allows for right-shifting the final answer of mon2 voltage measurements. allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the reading is weighted to the correct lsb.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 51 table 04h (table 01h in ds1859 configuration), 8fh: right-shift control factory default: 30h memory type: shadowed memory (see) 8fh reserved mon3 2 mon3 1 mon3 0 reserved bit7 bit0 control right shifts for the monitor channels. bit7 reserved bit6:4 mon3 2 -mon3 0 : allows for right-shifting the final answer of mon3 voltage measurements. allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the result so the reading is weighted to the correct lsb. this only applies to ?ine?conversions. bit3:0 reserved table 04h (table 01h in ds1859 configuration), 90h to 91h: reserved memory 90h to 91h reserved table 04h (table 01h in ds1859 configuration), 92h to 93h: gain calibration for v cc factory default: ####h memory type: shadowed memory (see) 92h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls gain of the v cc measurements. table 04h (table 01h in ds1859 configuration), 94h to 95h: gain calibration for mon1 factory default: ####h memory type: shadowed memory (see) 94h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 95h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls gain of the mon1 measurements. refer to the temperature monitor offset calibration section table 04h (table 01h in ds1859 configuration), 96h to 97h: gain calibration for mon2 factory default: ####h memory type: shadowed memory (see) 96h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 97h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls gain of the mon2 measurements.
DS1864 sfp laser controller and diagnostic ic 52 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), 98h to 99h: gain calibration for mon3 (fine) factory default: ####h memory type: shadowed memory (see) 98h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 99h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls gain of the mon3 fine measurements. table 04h (table 01h in ds1859 configuration), 9ah to 9bh: gain calibration for mon3 (coarse) factory default: ####h memory type: shadowed memory (see) 9ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 9bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 controls gain of the mon3 coarse measurements. table 04h (table 01h in ds1859 configuration), a2h to a3h: offset calibration for v cc factory default: ####h memory type: shadowed memory (see) a2h ss2 15 2 14 2 13 2 12 2 11 2 10 a3h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 controls offset of the v cc measurements. table 04h (table 01h in ds1859 configuration), a4h to a5h: offset calibration for mon1 factory default: ####h memory type: shadowed memory (see) a4h ss2 15 2 14 2 13 2 12 2 11 2 10 a5h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 controls offset of the mon1 measurements. table 04h (table 01h in ds1859 configuration), a6h to a7h: offset calibration for mon2 factory default: ####h memory type: shadowed memory (see) a6h ss2 15 2 14 2 13 2 12 2 11 2 10 a7h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 controls offset of the mon2 measurements.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 53 table 04h (table 01h in ds1859 configuration), a8h to a9h: offset calibration for mon3 (fine) factory default: ####h memory type: shadowed memory (see) a8h ss2 15 2 14 2 13 2 12 2 11 2 10 a9h 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 controls offset of the mon3 fine measurements. table 04h (table 01h in ds1859 configuration), aah to abh: offset calibration for mon3 (coarse) factory default: ####h memory type: shadowed memory (see) aah ss2 15 2 14 2 13 2 12 2 11 2 10 abh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit7 bit0 controls offset of the mon3 coarse measurements. table 04h (table 01h in ds1859 configuration), ach to adh: reserved memory ac h to adh reserved table 04h (table 01h in ds1859 configuration), aeh to afh: offset calibration for temperature factory default: ####h memory type: shadowed memory (see) aeh s2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit7 bit0 controls offset of the temperature measurements.
DS1864 sfp laser controller and diagnostic ic 54 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), b0h to b7h: thresholds for high-bias alarm flags (hbal) factory default: ffh memory type: shadowed memory (see) b0h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b5h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b6h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 these represent the high thresholds for comparing bias levels. each alarm byte contains the value for the threshold correspondi ng to the temperature range indicated below. only the upper 8 bits of the 16 bit measurement are compared here. b0h alarm byte location when temperature is less than -8?. b1h alarm byte location when temperature in the range of -8? to +8?. b2h alarm byte location when temperature in the range of +8? to +24?. b3h alarm byte location when temperature in the range of +24? to +40?. b4h alarm byte location when temperature in the range of +40? to +56?. b5h alarm byte location when temperature in the range of +56? to +72?. b6h alarm byte location when temperature in the range of +72? to +88?. b7h alarm byte location when temperature is greater than +88?.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 55 table 04h (table 01h in ds1859 configuration), b8h to bfh: thresholds for high-bias warning flags (hbwa) factory default: ffh memory type: shadowed memory (see) b8h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bbh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bfh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 these represent the high thresholds for comparing bias levels. each warning byte contains the value for the threshold corresponding to the temperature range indicated below. only the upper 8 bits of the 16 bit measurement are compared here. b8h warning byte location when temperature is less than -8?. b9h warning byte location when temperature in the range of -8? to +8?. bah warning byte location when temperature in the range of +8? to +24?. bbh warning byte location when temperature in the range of +24? to +40?. bch warning byte location when temperature in the range of +40? to +56?. bdh warning byte location when temperature in the range of +56? to +72?. beh warning byte location when temperature in the range of +72? to +88?. bfh warning byte location when temperature is greater than +88?. table 04h (table 01h in ds1859 configuration), c0h: reserved memory c 0h reserved
DS1864 sfp laser controller and diagnostic ic 56 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), c1h: pw2 password write-enable byte factory default: 00h memory type: shadowed memory (see) c1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte configures the write protection of pw2. this is discussed in more detail in the memory protection and password section. bit7 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers d0h through d6h in the main device memory, table 05h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit6 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 05h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit5 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers 80h through c7h in the main device memory, table 04h (table 01h in ds1859 configuration), table 02h, and table 03h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit4 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit3 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers 80h through f7h in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit2 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers 00h through 7ah in the main device memory. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit1 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers 80h through ffh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit0 when this bit is set, pw2 write protection is enabled for the memory block consisting of registers 00h through 7fh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level).
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 57 table 04h (table 01h in ds1859 configuration), c2h: pw2 password read-enable byte factory default: 00h memory type: shadowed memory (see) c2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte configures the read protection of pw2. this is discussed in more detail in the memory protection and password section. bit7 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers d0h through d6h in the main device memory, table 05h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit6 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 05h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit5 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers 80h through c7h in the main device memory, table 04h (table 01h in ds1859 configuration), table 02h, and table 03h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit4 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit3 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers 80h through f7h in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit2 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers 00h through 7ah in the main device memory. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit1 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers 80h through ffh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level). bit0 when this bit is set, pw2 read protection is enabled for the memory block consisting of registers 00h through 7fh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw2 level). 1 = memory is protected (pw2 level).
DS1864 sfp laser controller and diagnostic ic 58 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), c3h to c6h: pw2 password setting factory default: 0000 0000h memory type: shadowed memory (see) c3h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 c4h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 c5h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 c6h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 these four bytes contain the password for access to memory space that is protected per password enable bytes c1h and c2h of table 04h (table 01h in ds1859 configuration). (see memory protection and password section). table 04h (table 01h in ds1859 configuration), c7h: table select power-up default factory default: 01h memory type: shadowed memory (see) c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte is automatically loaded into the table select sram byte 7fh (lower memory) on power up.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 59 table 04h (table 01h in ds1859 configuration), dah: control and shutdown configuration and status factory default: 00h memory type: shadowed memory (see) dah fp o l h tx p enab l eh bal enab l eltx p enab l e x x x m as k bit7 bit0 this byte contains bits for shutdown configuration and status control. bit7 fpol: configures the polarity of the auxiliary shutdown (fetg output). 0 = fetg is asserted low under a shutdown condition. 1 = fetg is asserted high under a shutdown condition. bit6 htxp enable: configures a shutdown in response to a htxp alarm. 0 = shutdown will not respond to a trip of htxp alarm. 1 = shutdown will respond to a trip of htxp alarm. bit5 hbal enable: configures a shutdown in response to a hbal alarm. 0 = shutdown will not respond to a trip of hbal alarm. 1 = shutdown will respond to a trip of hbal alarm. bit4 ltxp enable: configures a shutdown in response to a ltxp alarm. 0 = shutdown will not respond to a trip of ltxp alarm. 1 = shutdown will respond to a trip of ltxp alarm. bit3:1 not used. bit0 m a sk : c onfi g ur es l ocati ons of al ar m s and w ar ni ng i nter r up t m asks to b e ei ther i n tab l e 05h or i n tab l e 01h ( tab l e 00h i n d s 1859 confi g ur ati on) . 0 = inter r up t m asks ar e l ocated i n tab l e 05h, b ytes f8h thr oug h fbh. 1 = inter r up t m asks ar e l ocated i n tab l e 01h ( tab l e 00h i n d s 1859 confi g ur ati on) , b ytes f8h thr oug h fbh. table 04h (table 01h in ds1859 configuration), dbh: high transmitted power threshold (htxp) factory default: ffh memory type: shadowed memory (see) dbh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte sets a high d/a threshold for comparing transmitted power level. only the upper 8 bits of the 16 bit value are compar ed. table 04h (table 01h in ds1859 configuration), dch: low transmitted power threshold (ltxp) factory default: 00h memory type: shadowed memory (see) dch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte sets a low d/a threshold for comparing transmitted power level. only the upper 8 bits of the 16 bit value are compare d.
DS1864 sfp laser controller and diagnostic ic 60 ____________________________________________________________________ table 04h (table 01h in ds1859 configuration), ddh: los threshold (los) factory default: 00h memory type: shadowed memory (see) ddh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte sets a low d/a threshold for comparing received power (rssi) level. only the upper 8 bits of the 16 bit value are compared. table 05h, c0h to c1h: device id factory default: 18 64h memory type: hardwired c0h 00011000 c1h 01100100 bit7 bit0 these bytes identify the device as a DS1864. table 05h, c2h: device revision factory default: ##h memory type: hardwired c2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte indicates revision of the design. table 05h register descriptions
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 61 table 05h, d1h: pw1 password write-enable byte factory default: 00h memory type: shadowed memory (see) d1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte configures the write protection of pw1. this is discussed in more detail in the memory protection and password s ection. bit7 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers d0h through d6h in the main device memory, table 05h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit6 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 05h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit5 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers 80h through c7h in the main device memory, table 04h (table 01h in ds1859 configuration), table 02h, and table 03h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit4 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit3 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers 80h through f7h in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit2 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers 00h through 7ah in the main device memory. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit1 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers 80h through ffh in the auxiliary device memory on i 2 c slave address a0h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit0 when this bit is set, pw1 write protection is enabled for the memory block consisting of registers 00h through 7fh in the auxiliary device memory of i 2 c slave ddress a0h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level).
DS1864 sfp laser controller and diagnostic ic 62 ____________________________________________________________________ table 05h, d2h: pw1 password read-enable byte factory default: 00h memory type: shadowed memory (see) d2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 this byte configures the read protection of pw1. this is discussed in more detail in the memory protection and password section. bit7 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers d0h through d6h in the main device memory, table 05h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit6 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 05h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit5 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers 80h through c7h in the main device memory, table 04h (table 01h in ds1859 configuration), table 02h, and table 03h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit4 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers f8h through ffh in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit3 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers 80h through f7h in the main device memory, table 01h (table 00h in ds1859 configuration). 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit2 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers 00h through 7ah in the main device memory. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit1 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers 80h through ffh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level). bit0 when this bit is set, pw1 read protection is enabled for the memory block consisting of registers 00h through 7fh in the auxiliary device memory of i 2 c slave address a0h. 0 = memory is unprotected (pw1 level). 1 = memory is protected (pw1 level).
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 63 table 05h, d3h to d6h: pw1 password setting factory default: 0000 0000h memory type: shadowed memory (see) d3h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 d4h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 d5h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 d6h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit7 bit0 these four bytes contain the password for access to memory space that is protected per password enable byte d1 and d2h of table 05h (see memory protection and password section).
DS1864 sfp laser controller and diagnostic ic 64 ____________________________________________________________________ table 05h, f8h: alarm masks factory default: 00h memory type: shadowed memory (see) f8h tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 these bytes configure a maskable interrupt, determining which alarm flags assert the mint bit (lower memory, byte 71h, bit 0). if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which of these mask sets are used to generate the mint interrupt. bit7 tmpalmhimask: determines if an interrupt is generated for a high-temperature alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 tmpalmlomask: determines if an interrupt is generated for a low-temperature alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5 v cc almhimask: determines if an interrupt is generated for a high v cc alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit4 v cc almlomask: determines if an interrupt is generated for a low v cc alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit3 mon1almhimask: determines if an interrupt is generated for a high mon1 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit2 monalmlomask: determines if an interrupt is generated for a low mon1 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit1 mon2almhimask: determines if an interrupt is generated for a high mon2 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit0 mon2almlomask: determines if an interrupt is generated for a low mon2 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 65 table 05h, f9h: alarm masks factory default: 00h memory type: shadowed memory (see) f9h mon3hi mon3lo reserved bit7 bit0 these bytes configure a maskable interrupt, determining which alarm flags assert the mint bit (lower memory, byte 71h, bit 0). if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which mask sets are used to generate the mint interrupt. bit7 mon3almhimask: determines if an interrupt is generated for a high mon3 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 mon3almlomask: determines if an interrupt is generated for a low mon3 alarm flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5:0 reserved.
DS1864 sfp laser controller and diagnostic ic 66 ____________________________________________________________________ table 05h, fah: warning masks factory default: 00h memory type: shadowed memory (see) fah tmphi tmplo v cc hi v cc lo mon1hi mon1lo mon2hi mon2lo bit7 bit0 these bytes configure a maskable interrupt, determining which warning flags assert the mint bit (lower memory, byte 71h, bit 0) . if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. the mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which mask sets are used to generate the mint interrupt. bit7 tmpwrnhimask: determines if an interrupt is generated for a high-temperature warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 tmpwrnlomask: determines if an interrupt is generated for a low-temperature warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5 v cc wrnhimask: determines if an interrupt is generated for a high v cc warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit4 v cc wrnlomask: determines if an interrupt is generated for a low v cc warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit3 mon1wrnhimask: determines if an interrupt is generated for a high mon1 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit2 monwrnlomask: determines if an interrupt is generated for a low mon1 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit1 mon2wrnhimask: determines if an interrupt is generated for a high mon2 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit0 mon2wrnlomask: determines if an interrupt is generated for a low mon2 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 67 table 05h, fbh: warning masks factory default: 00h memory type: shadowed memory (see) fbh mon3hi mon3lo reserved bit7 bit0 these bytes configure a maskable interrupt, determining which warning flags assert the mint bit (lower memory, byte 71h, bit 0) . if one of the interrupts is desired, its bit must be written to a 1 here. if no interrupt is desired, the bit should be written to a 0. a mask configuration bit (table 04h (table 01h in ds1859 configuration), register dah, bit 0) determines which mask sets are us ed to generate the mint interrupt. bit7 mon3wrnhimask: determines if an interrupt is generated for a high mon3 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit6 mon3wrnlomask: determines if an interrupt is generated for a low mon3 warning flag. 0 = no interrupt is generated. 1 = an interrupt is generated. bit5:0 reserved.
DS1864 sfp laser controller and diagnostic ic 68 ____________________________________________________________________ i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. when the bus is idle, it often initi- ates a low-power (or idle) mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing diagrams for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagrams for applicable timing. repeated start condition: the master can use a repeat- ed start condition at the end of one data transfer to indi- cate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condi- tion is issued identically to a normal start condition. see the timing diagrams for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (figure 19). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (figure 19) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock puls- es, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledge- ment (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a 1 during the 9th bit. timing (figure 19) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minate communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte con- tains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS1864 (and some of its predecessors) is unique in that it actu- ally responds to two slave addresses. the slave address for the auxiliary device memory is a0h. the slave address for the main device memory is a2h by default, although it can be programmed to something different by writing byte 8ch in table 04h (table 01h in ds1859 configuration) along with the corresponding configuration bit. by writing the correct slave address with r/ w = 0, the master indicates it will write data to the slave. if r/ w = 1, the master will read data from the slave. if an incorrect slave address is written, the DS1864 assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. if both the auxiliary device and the main device addresses are set to a0h, only the main device will respond. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte.
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 69 i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the DS1864 writes 1 to 8 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8- byte page (one row of the memory map). the first page begins at address 00h and subsequent pages begin at multiples of 8 (08h, 10h, 18h, etc). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start con- dition, and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom page is written, the DS1864 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the DS1864 will not acknowledge either of its slave addresses because it is busy. it is possible to take advantage of that phenomenon by repeatedly address- ing the DS1864, which allows the next page to be writ- ten as soon as the DS1864 is ready to receive the data. the alternative to acknowledge polling is to wait for maximum period of t w to elapse before attempting to write again to the DS1864. eeprom write cycles: when eeprom writes occur, the DS1864 writes the whole eeprom memory page (8 bytes), even if only a single byte on the page was modi- fied. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified dur- ing the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page one byte at a time wears the eeprom out eight times faster than writing the entire page at once. the DS1864? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. writing to sram- shadowed eeprom memory with see = 1 does not count as an eeprom write. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular address. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it nacks to indicate the end of the transfer and generates a stop condition. this can be done with or without modifying the address counter? location before the read cycle. the DS1864? address counter does not wrap on page boundaries during read operations, but the counter will roll from its uppermost memory address ffh to 00h if the last memory location is read during the read transaction. see figure 20 for a read example using the repeated start condition to specify the starting memory location. application information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open collector output on the DS1864 that requires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be utilized
DS1864 sfp laser controller and diagnostic ic 70 ____________________________________________________________________ for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the ac electrical characteristics table are within specification. stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 18. i 2 c data transfer protocol sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 19. i 2 c ac characteristics
DS1864 sfp laser controller and diagnostic ic ____________________________________________________________________ 71 xxxxxxxx 101 0 00 0 0 101 0 10 0 0 101 0 00 0 0 101 0 01 0 0 101 0 11 0 0 101 0 10 0 0 communications key write a single byte to 2-wire address a0h write up to a 8-byte page with a single transaction i 2 c address a2h read a single byte with a dummy write cycle to set the address counter from i 2 c address a0h read multiple bytes with a dummy write cycle to set the address counter from i 2 c address a2h 8-bits address or data white boxes indicate the master is controlling sda the first byte sent after a start condition is always the slave address followed by the read/write bit. shaded boxes indicate the slave is controlling sda start ack not ack s s s s s a a a a a a a p a asr sr a a a p n p n p a a data data data data data data data memory address memory address memory address memory address data aa a pn sr stop repeated start note: all bytes are sent most significant bit first. figure 20. i 2 c communications examples
DS1864 sfp laser controller and diagnostic ic maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 72 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. springer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 72 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 72 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip topology transistor count: 52353 substrate connected to ground sda scl 4.7k ? rsel inlos tx-d rx-los intx-f v cc dac1 mon1p mon2 mon1n gnd dac0 mon3n fetg mon3p rselout out1 tx-f in1 host 3.3v 3.3v 0.1 f apcset modset laser driver intx-f out+ bias md tx-disable receiver signal + tx-disable (if single ended) tx_disable pc_mon tx-fault bc_mon DS1864 max3975 4.7k ? 3.3v 10nf 10k ? 3.3v 10k ? 3.3v 10k ? 3.3v 10k ? 3.3v 10 ? rosa 1k ? 1k ? typical operating circuit

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